Nano-X Imaging has been granted a patent for a method to fabricate silicon die stacks for electron emitter chips. The process involves sintering a silicon substrate die to other die layers using metal powder, a chip carrier, and heated compression, ensuring conductive coupling between bonding pads. GlobalData’s report on Nano-X Imaging gives a 360-degree view of the company including its patenting strategy. Buy the report here.
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According to GlobalData’s company profile on Nano-X Imaging, Computed tomography was a key innovation area identified from patents. Nano-X Imaging's grant share as of July 2024 was 24%. Grant share is based on the ratio of number of grants to total number of patents.
Method for fabricating silicon die stacks for electron emitters
The patent US12027489B2 outlines a method for fabricating a field emitter array, which involves several key steps. Initially, a silicon substrate die with a bonding surface is obtained, along with a chip carrier that features an electric circuit and wire bonding surfaces. The process includes applying a metal powder—specifically silver particles sized at 100 nanometers—to the bonding surface of the die. This metal powder is then covered with the chip carrier, and the assembly is compressed between two heated plates. The method emphasizes the importance of conductively coupling the bonding pads of the die to the corresponding pads of the chip carrier, which can be achieved through wire bonding. The heating process is carefully controlled to ensure the metal powder reaches a temperature above its bonding temperature but below its melting point, with specific parameters such as a pressure of 10-8 Torr maintained for 10 minutes.
Additionally, the patent describes variations of the fabrication method, including the use of an integrated circuit chip with a gold-coated silicon base and a chip carrier that also has a gold-coated upper side. The application of the metal powder in this scenario follows similar principles, with the powder being dispensed to a required thickness and volume, potentially using a syringe. The process culminates in compressing the integrated circuit chip and chip carrier between heated plates to achieve a bonded assembly. The claims also highlight the option of applying multiple layers of metal powder during the bonding process, further enhancing the structural integrity and functionality of the field emitter array. Overall, the patent presents a detailed methodology aimed at improving the fabrication of field emitter arrays through precise material application and controlled bonding techniques.
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GlobalData Patent Analytics tracks bibliographic data, legal events data, point in time patent ownerships, and backward and forward citations from global patenting offices. Textual analysis and official patent classifications are used to group patents into key thematic areas and link them to specific companies across the world’s largest industries.
